While the industry is still competing on TOPS (Top-of-PSG) computing power and stacking HBM (High-Performance Multiprocessor) memory, Silicon Valley startup Architect Labs has delivered Redwood: the world’s first AI inference accelerator chip designed, verified, and developed end-to-end by AI. Only two human engineers provided the high-level requirements specifications, the AI system completed the entire hardware chain in 14 days, and modifications were completed within 48 hours, resulting in zero functional bugs on the first FPGA deployment and 95% module verification coverage.
It’s not a giant chip designed for large-scale training in data centers, but rather a low-power, large-model inference accelerator targeting robotics, smart home local AI hubs, drones, and edge physical AI scenarios. Its biggest controversy and highlights stem half from the hardware architecture itself and the other half from the new development paradigm of “AI-made chips.”
Hardware Architecture: Tile Spatial Data Flow for Low-Latency Edge Inference in Single Batches
Redwood employs a scalable tile spatial data flow architecture. Internally, the chip consists of numerous identical compute tiles, an on-chip network (NoC), a DMA controller, and a shared SRAM memory pool. Each tile integrates a RISC-V control core, a systolic matrix computation array, a SIMD vector engine, and 512KB of local SRAM. The entire Transformer inference operator suite (matrix multiplication, KV cache, softmax, attention, dynamic quantization) is implemented natively in hardware, eliminating heavy reliance on host CPU assistance. The complete inference chain is completed in a closed loop within the chip using architectl....
- The on-chip network employs a credit-based flow control mechanism, supporting broadcast and multicast, and direct data transfer between tiles, reducing memory wall overhead caused by repeated read/write operations to external DDR memory.
- Softmax operators reuse SIMD units, avoiding the need for dedicated hardware modules, thus reducing chip area; Redwood Nano’s estimated NPU core area on Samsung’s 8nm process is only 2.88mm², achieving extremely high area utilization.
- The FPGA verification version operates at 250MHz; if tapered as an ASIC, the target frequency can reach 1GHz, with a total power consumption of approximately 1W, focusing on low-power single-batch real-time inference, not high-throughput, high-concurrency applications.
- Supports Llama and Qwen series open-source large models; FPGA prototype testing shows Qwen3-0.6B can reach 12.1 tokens/s, meeting the real-time dialogue needs of local agents, home hubs, and robot endpoints (architectl…).
Performance Benchmark: Benchmarked against NVIDIA Jetson Orin Nano using the same 8nm process; Predicted Data: Throughput increased by 1.75x, power consumption decreased by 1.9x, energy efficiency improved by 3.4x. Note: These figures are based on FPGA test results extrapolated to ASIC theoretical values, not actual silicon wafer test results.
Two Core Values: The Hardware Itself, and the AI-Driven Chip Design Paradigm
1. Edge Inference Hardware Value: Tailor-made for Physical AI Scenarios
Redwood’s positioning is very focused: single-batch, low-power, ultra-low-latency physical AI inference, targeting edge hardware such as whole-house local AI hubs, humanoid robots, robot vacuums, drones, and smart cameras, rather than cloud training servers.
Many edge NPUs in the industry suffer from a pain point: the hardware is a general design, Transformer operator adaptation relies on software patching, operator splitting and KV caching have high overhead, and the token speed for running small-parameter, large-model processes is relatively low. Redwood’s hardware and software are entirely generated collaboratively by AI. Operators, firmware, computing kernels, and hardware architecture are deeply co-optimized, with native adaptation for Transformer inference. It runs billion-parameter models at watt-level power consumption, perfectly aligning with the current trend of large-scale local models in smart homes and AI agents for robots.
Imagine its application: future home AI hubs like the Mi AI Cube and LG ThinQ ON, or DJI robot hardware, equipped with Redwood-like chips, can perform large-scale local model scheduling at 1-2W power consumption, reducing heavy reliance on the cloud. The architecture also supports expansion, allowing it to be used as a small edge SoC or assembled into a Chiplet chipset to further extend its computing power.
(Note: The last line appears to be a separate, unrelated statement and is left untranslated.) ### 2. Paradigm Revolution: AI Autonomously Completes the Entire Chip Design Chain
Traditional AI chip development process: Teams of dozens or even hundreds of people, from architecture definition, RTL coding, simulation verification, formal verification, firmware drivers, often taking 1-2 years and costing tens of millions of dollars. Once the AI model algorithm iterates, hardware specifications are difficult to adjust quickly, and the hardware iteration speed cannot keep up with the model iteration speed.
Project Redwood: Humans only output high-level requirements documents in natural language; the remaining RTL code, UVM verification environment, formal verification, firmware, drivers, and operator kernels are all automatically generated by AI. When requirements change, the entire set is regenerated, verified, and deployed on hardware within 48 hours. At peak development, AI automatically submitted 115 hardware code changes daily, and the first deployment of the FPGA had zero functional defects—a record almost impossible to achieve in traditional semiconductor engineering.
More attention-grabbing is the recursive closed loop: AI models running on Redwood have been used to iterate the specifications of next-generation chips, forming a self-itergencing loop of “AI chip – running AI – designing next-generation AI chip,” an exploration never before seen on a large scale in the semiconductor industry.
Advantages from a Real-World Perspective
- High Theoretical Upper Limit of Edge Energy Efficiency. Designed for full-stack collaborative design of Transformer inference, eliminating redundant hardware units, it runs billion-parameter models at watt-level power consumption, making it highly suitable for power-constrained hardware such as smart homes, robots, and drones, aligning with the trend of large-scale local models on the edge.
- Disruptive Development Iteration Speed. Requirements changes can be completed within 48 hours for a complete hardware iteration. Small teams can also quickly customize dedicated AI acceleration hardware, breaking down the traditional manpower and time barriers in chip R&D, which is of great significance to hardware startups.
- Completely On-Chip Closed Loop Inference Thread. KV caching, attention, and quantization are all processed internally by the chip, with extremely low CPU resource consumption on the host machine. It can be embedded in small embedded devices without requiring a powerful main processor.
- Flexible Architecture Scalability. The Tile grid architecture allows for scalability, supporting both millimeter-scale edge NPUs and chipplet stacking for expanded computing power, covering a range from smart home hardware to mid-sized inference servers.
Unavoidable Shortcomings and Risks in the Prototype Stage
- ASIC Tape-out and Mass Production Not Yet Completed. All performance data is derived from AMD FPGA platform simulations, without actual silicon wafer testing. FPGAs and ASICs differ; power consumption, frequency, and actual energy efficiency may deviate after tape-out. The 3.4x energy efficiency improvement is a prediction, not actual silicon wafer results.
- Highly Specific Scenarios. It excels only at single-batch inference, geared towards local agent interactions; unsuitable for high-concurrency multi-user inference in the cloud, completely abandoning training capabilities, resulting in far lower versatility than GPUs. Performance gains will be significantly reduced when running non-Transformer models.
- Almost No Software Ecosystem. There is no mature compilation stack, toolchain, or CUDA-like software ecosystem. Currently, only open-source models with AI-generated kernels can run; migrating models is costly for third-party developers, and a complete software toolchain is necessary for commercial deployment.
- The reliability of AI-generated hardware remains unknown in the long term. Although 95% verification coverage and zero defects on the FPGA have been achieved at present, long-term chip stability, timing issues under extreme temperatures, aging problems, and whether the AI generation logic harbors hidden boundary bugs still require long-term silicon verification.
- The timeline for commercial deployment is unclear. Architect Labs has only publicly released academic prototypes and has not disclosed tape-out plans, mass production timelines, or commercialization roadmaps. It is unlikely to appear in consumer smart home or robotic hardware in the short term.
Competitive Product Comparison
| Product | Redwood (Nano Inference) | NVIDIA Jetson Orin Nano | Mainstream Domestic Edge NPUs |
| Positioning | Low-power single-batch large model inference, physics AI | General-purpose edge GPU, inference + limited training | Primarily edge AI vision, also supporting large models |
| Development Method | AI end-to-end automatic generation of RTL/verification/firmware | Traditional hardware development by hundreds of people | Traditional hardware engineering process |
| Process Technology | Estimated Samsung 8nm | Samsung 8nm | 8-12nm |
| Power Consumption | ASIC estimated at approximately 1W | 7-10W | 2-5W |
| Core Advantages | Native Transformer co-optimization, fast iteration speed | Complete CUDA ecosystem, strong versatility | Mature toolchain, compatible with domestic ecosystem |
| Weaknesses | No ASIC, no software ecosystem, only prototype | Relatively high power consumption | Large-Model Inference Operator Adaptability is Generally Poor |
Summary: Its significance lies not in replacing GPUs, but in rewriting the logic of hardware manufacturing.
Redwood offers the industry two layers of inspiration: First, the hardware itself—a low-power Transformer inference accelerator for robots and whole-house AI home hardware, perfectly matching the current needs of local AI hubs and physical agent hardware in the home; second, and more importantly, a new paradigm for AI-designed chips.
In the past, the pace of hardware iteration was determined by human chip engineers, with AI model iterations far outpacing hardware iterations. Redwood demonstrates a possibility: future hardware specifications can iterate rapidly along with AI models, and small teams can quickly customize dedicated AI acceleration hardware.
However, we must soberly distinguish between academic prototypes and commercial products: Redwood is currently still a laboratory product; its energy efficiency advantage remains at the level of simulation; its software ecosystem is lacking; and it is still a long way from large-scale adoption in robotic vacuum cleaners and AI home hubs. In the short term, it will not disrupt Nvidia or the existing edge NPU landscape, but it represents a highly imaginative path for future edge AI hardware.